It makes sense that the standard governing AI accelerators should release an update less than a year after its first iteration.
Ultra Accelerator Link (UALink) 1.0 was released in April 2025, and the UALink consortium just released a major update to the specification that addresses in-network compute, chiplet definition, and manageability. These additions will support the deployment of UALink solutions in multi-workload environments and help improve UALink technology efficiency, performance for AI workloads, and ease of implementation.
In a briefing with EE Times, Kurtis Bowman, UALink consortium board chair, said the evolution of UALink reflects the rapid growth of accelerators in data centers, where memory bandwidth is critical to performance. “The interconnect becomes a very strategic decision,” he said. “It really defines how fast you’re going to be able to get your tokens, how fast you can do your training, how fast you can do your inference.”
UALink was introduced as complementary to other critical interconnect standards such as Peripheral Component Interconnect Express (PCIe), Ethernet, Compute Express Link (CXL), and the Universal Chiplet Interconnect Express (UCIe). UALink facilitates interconnectivity between AI accelerators and hosts through various protocols, including CXL and PCIe.
The UALink consortium was founded in October 2024 with the rationale that accelerators needed their own focused, nimble, and open standard that would require more regular updates, given the fast pace of accelerator and GPU development. “We find ourselves in a nice stack,” Bowman said.
UALink is also purpose-built for scale-up AI fabrics, added Peter Onufryk, UALink Consortium president. “What we’ve done is a ground-up implementation that’s optimized for that specific use case.”
UALink Common Specification 2.0 adds in-network compute, which facilitates computation and communication between accelerators, while reducing latency, saving bandwidth, and improving scaling efficiency for distributed training and inference.
“There’s an opportunity for increased performance improvement by moving some compute functionality into the fabric itself,” Onufryk said. “We have an open solution for collectives in the industry.”
The UALink switches do part of the collective communication work themselves instead of treating all traffic as opaque packets between GPUs, which reduces latency.
Another change in this update is that the link layer and the physical layer have been broken out, Bowman said. “It really gives us the flexibility to move those independently.”
Splitting these allows the data link layer to focus on flit framing, CRC, retransmission, and flow control, while the physical layer handles electrical transmission and FEC details. The separation also enables UALink to update or add new physical interfaces and faster speeds with less disruption to the rest of the stack.
The UALink also takes advantage of standardized protocols, modeling, and APIs to improve manageability with centralized control and management planes, Bowman said. “We’re very quickly giving the industry something that they can use to implement UALink on existing designs and pick the right solution for their scale-up fabric.”
The addition of a UALink chiplet specification in collaboration with the UCIe consortium defines the necessary information to integrate UALink technology into chiplet-based SoCs, including interfaces, form factors, flow control, and chiplet management standardization.
Onufryk said this allows for building modular accelerators without being locked into a single supplier’s interconnect stack. “If you’re an accelerator company, you can focus on what you’re best at and not have to deal with all the analog and logical issues.”
Bowman said one of the next features to be added will be a compliance specification, which will be released later this year. The consortium will also hold a plugfest to ensure compatibility across switches and accelerators.
Bowman expects the rapid pace of development for UALink to continue. “As we look out into 2027, we think the industry will continue to morph very quickly,” he said. “We need to have specs ready.”
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